1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the management of write transactions within a memory interconnect that connects a shared memory and a plurality of transaction masters.
2. Description of the Prior Art
It is known to provide data processing systems that include a shared memory and a plurality of transaction masters. Such arrangements are often found within system-on-chip integrated circuits. Within such systems the different transaction masters can each generate write transactions which write data values into the address space of the shared memory. The shared memory can be accessed by more than one transaction master.
It is also known within such systems that a transaction master may include a local cache memory. Providing a local cache memory within a transaction master increases the speed and efficiency of that transaction master. Cache memories typically provide higher speed access to data with a lower energy cost.
However, a problem with providing local cache memories within such systems is that multiple copies of data from a given memory address are present. For example, a given line of data (a plurality of bytes of data) may be present both within a given range of addresses of the shared memory and in a line of a local cache memory corresponding to those addresses within the shared memory. When multiple copies of data for the same memory addresses exist within the system, then mechanisms may be required to ensure the coherency of those different copies. As an example, if the version of the data stored within a local cache is updated, then this updated data will be the most up-to-date copy of the data for those memory addresses within the system. Should a different transaction master then seek to read data from the shared memory at addresses corresponding to those which have been updated in the locally cached copy, then the shared memory would, without coherence mechanisms in place, return an out-of-date copy of the data concerned. In order to deal with this problem, it is known to provide coherency mechanisms, such as snoop mechanisms, within coherent memory systems which include a shared memory and one or more local cache memories.
One way in which such coherence mechanisms may work concerns the management of write transactions. If a transaction master seeks to make a write back to the shared memory, then the coherence mechanisms may issue snoop requests to any local cache memories within the system which could be holding a copy of the line of data to which the write transaction is being made. If any of such local cache memories holds a more up-to-date version of the line of data than is held within the shared memory, then this more up-to-date version of the line of data should be written back to the shared memory before the write transaction then is made to that shared memory.
This ensures that a hazard condition does not arise in which the write transaction is inappropriately first made to the shared memory and then is overwritten when the line of data stored within one of the local cache memories and overwrites what may be a more up-to-date version of that line of data, i.e. the coherency mechanism ensure the ordering in time of the write transactions to the shared memory is maintained. In order to avoid this possibility, a write to a line of data within the shared memory can be stalled or buffered within the memory interconnect until the coherency mechanisms can ensure that any copies of that line of data held within local caches within the system, and that are more up-to-date than the copy in the shared memory, have been written back to the shared memory. The stalled or buffered write transaction can then proceed to write to the shared memory as the writes to the shared memory will then occur in the correct order. While this approach has the advantage of ensuring memory consistency and correctness, it has the disadvantage of requiring buffer storage within the memory interconnect or the stalling of the transaction master which generated a stalled write request.